sit15 79 1.2mm 2 power, low - jitter, 1hz C 2.5 mhz oscillator rev. 1.1 october 12, 2017 www.sitime.com features ? 1 hz to 2.5 mhz 50 ppm all-inclusive frequency stability ? factory programmable output frequency ? worlds smallest oscillator footprint: 1.2 mm 2 ? 1.5 x 0.8 mm csp ? no external bypass cap required ? improved stability reduces system power with fewer network timekeeping updates ? ultra-low power: 6 a (100 khz) ? supply voltage range: 1.62 v to 3.63 v ? operating temperature ranges: -20c to +70c, -40c to +85c ? pb -free, rohs and reach compliant application s ? health and wellness monitors ? smart pens ? ulp input devices ? proprietary wireless ? sensor interface electrical characteristics conditions: min/max limits are over temperature, v dd = 1.8v 10%, unless otherwise stated. typicals are at 25c and v dd = 1.8v. table 1. electrical characteristics parameter symbol min. typ. max. unit condition frequency and stability output frequency f out 1 2.5 m hz initial frequency tolerance f_tol - 10 10 ppm includes 2x reflow frequency stability f_stab - 50 50 ppm all inclusive of over temperature, referenced to nominal frequency at 25c, inclusive of v dd , aging, and load jitter performance integrated phase jitter ipj 2 3 .5 ns rms f out > 1 khz. integration bandwidth = 100 hz to f out /2. inclusive of 50 mv peak - to - peak sinusoidal noise on v dd . noise frequency 100 hz to 20 mhz rms period jitter pj 2.2 4 .5 ns rms cycles = 10,000, f = 100khz. per jedec standard 65b, tested at 100khz . see performance plot for other freq uencies. supply voltage and current consumption operating supply voltage v dd 1.62 3.63 v no load supply current i dd 3.6 5 5 a f out = 1 hz 4.5 5.5 f out = 33 khz 6 7 f out = 100 khz 13 16 f out = 1 mhz 33 40 f out = 2 mhz start - up time at power - up t_start 150 300 ms measured when supply reaches 90% of final v dd to the first output pul se and within specified min/max frequency limit. 300 + 2. 0 cycles 300 + 2.5 cycles 10 hz < f out 200 hz, to first output pulse . measured when supply reaches 90% of final v dd to the first output pul se and within specified min/max frequency limit. 500 + 3 cycles 1 hz f out 10 hz, to first output pulse. measured when supply reaches 90% of final v dd to the first output pul se and within specified min/max frequency limit. operating temperature range operating temperature range op_temp - 20 70 c c ordering code - 40 85 c i ordering code lvcmos output output rise/fall time t r , t f 9 20 ns 20 - 80%, 15 pf load, v dd = 1.8v +/ - 10% output clock duty cycle dc 45 55 % output voltage high voh 90% v dd i oh = - 50 a, 15 pf load output voltage low vol 10% v dd i ol = 50 a, 15 pf load note: 1. includes initial tolerance, over temp stability, 2x reflow, v dd range, board-level underfill, and 20% load variation. tested with agilent 53132a frequency counter. measured with 100 ms gate time for accurate frequency measurement.
SIT1579 1.2mm 2 power, low - jitter, 1hz 2.5 mhz oscillator rev. 1.1 page 2 of 8 www.sitime.com table 2 . pin configuration table 3 . absolute maximum ratings attempted operation outside the absolute maximum ratings may cause permanent damage to the part. actual performance of the ic is only guaranteed within the operational specifications, not at absolute maximum ratings. parameters test conditions value unit continuous power supply voltage range ( v dd ) - 0.5 to 4.0 v continuous maximum operating temperature range 105 c short duration maximum operating temperature range ? minutes 125 c human body model (hbm) esd protection jesd22 - a114 2000 v charge - device model (cdm) esd protection jesd22 - c101 750 v machine model (mm) esd protection jesd22 - a115 300 v latch - up tolerance jesd78 compliant mechanical shock resistance mil 883, method 2002 20,000 g mechanical vibration resistance mil 883, method 2007 70 g 1508 csp junction temperature 150 c storage temperature - 65 to 150 c system block diagram figure 2 . SIT1579 block diagram pin symbol i/o functionality 1 nc internal test no connect. leave floating. pin 1 is for internal testing and is designed to be left floating. 2 clk out out oscillator clock output. 3 v dd power supply operates from nominal supply voltages between 1.8v and 3.3v. und er normal operating conditions, v dd does not require external bypass/decoupling capacitor(s). SIT1579 includes on - chip v dd filtering. 4 gnd power supply ground connect to ground. top view figure 1 . pin assignment control temp - to - digital nvm prog prog driver nc gnd g n d v d d c l k o u t n c 1 4 2 3
SIT1579 1.2mm 2 power, low - jitter, 1hz 2.5 mhz oscillator rev. 1.1 page 3 of 8 www.sitime.com description SIT1579 is an ultra - small and ultra - low power factory programmable oscillator with an output f requency range between 1 hz to 2.5 0 + ] 6 l 7 l p h ? v v l o l f r q 0 ( 0 6 w h f k q r o r j \ enables the first programmable, power oscillator l q w k h z r u o g ? v smallest footprint and chip - sca le packaging (cs p). ty pical supply current is only 6 a (100 khz) . sitime's mems oscillator consists of a mems resonator and a programmable analog circuit. SIT1579 mems resonator is built z l w k 6 l 7 l p h ? v x q l t x h 0 ( 0 6 ) l u v w ? s u r f h v v $ n h \ p d q x i d f w x u l q j v w h s l v ( s l 6 h d o ? g x u l q j z k l f k w k h 0 ( 0 6 resonator is annealed with temperatures over 1000c. episeal creates an extremely strong, clean, vacuum chamber that encapsulates the mems resonator and ensures the best performance and reliability. during episeal, a poly silicon cap is grown on top of the resonator cavity, which eliminates the need for additional cap wafers or other exotic packaging. as a result, 6 l 7 l p h ? v 0 ( 0 6 u h v r q ator die can be used like any other v h p l f r q g x f w r u g l h 2 q h x q l t x h u h v x o w r i 6 l 7 l p h ? v 0 ( 0 6 ) l u v w and episeal manufacturing processes is the capability to l q w h j u d w h 6 l 7 l p h ? v 0 ( 0 6 g l h z l w k d 6 2 & |